Electrostatic Discharge or ESD is a well-known cause of failure for electronic and electro-optical components. The most commonly referenced test standards address simulation of the ESD event that can be produced by handling or touching of the parts by a person who has an electrostatic charge on his or her body. This type of ESD simulation testing is referred to as HBM or Human Body Model testing. This Newsletter will discuss some of the differences among the various ESD (HBM) standards, but the standards themselves should be reviewed thoroughly to get a good understanding of the requirements.

Other test standards have been developed around a Charged Device Model (CDM), a Machine Model (MM) and a Field Induced Model (FIM). These are also important considerations within the industry, but are not discussed in this newsletter.

Human Body Model (HBM) testing is performed with an RC (Resistor/Capacitor) circuit to produce current pulses which simulate ESD strikes on the components. The shape of the current pulse (rise time, ringing, etc.) is tightly specified by the standards to assure repeatable results that can be used to compare the relative sensitivity levels of different products.

The primary purpose of ESD (HBM) testing is to determine the threshold level of voltage that will cause failure of a component, or alternately, the “withstand voltage” (the highest voltage that can be applied without causing failure). Some of the standards use the withstand voltage to classify components according to their relative sensitivity levels (Class 0, Class1, etc.). Be careful in quoting ESD classification levels, because the various standards do not agree on the voltage levels that fall within each class. Any reference to ESD classification must also refer to the standard that was used. While the standards provide methods to determine the threshold level, ESD testing is also sometimes used as a “go / no go” test to determine if a component will pass a predetermined stress level.

All the standards listed below specify the same basic current pulse for testing, with only minor differences in tolerances. However, the test methodology varies considerably from standard to standard, and can have a significant impact on the complexity and cost of testing.

Telcordia:

The ESD Threshold test specified by Telcordia GR-468-CORE, “Generic Reliability Assurance Requirements for Optoelectronic Devices Used in Telecommunications Equipment” allows the use of the test method specified in either TIA/EIA FOTP-129 or Telcordia TR-NWT-000870.

TIA/EIA FOTP-129 covers ESD stressing of packaged optoelectronic components (not purely electronic components). The scope of the procedure says “a packaged optoelectronic component includes assembled packages which contain one or more optoelectronic chips one or all of whose chip terminals are directly connected to the package terminals”. The standard seems to be most suitable for relatively simple components such as laser modules. It can be rather cumbersome for modules/devices with large pin counts because of the large number of pin combinations to be stressed. The individual chips in the package are intended to be stressed separately. Six samples are required, with three of them stressed with positive polarity and three with negative polarity. Each set of samples is stressed at sequentially higher voltage levels until one or more failures occur.

TR-NWT-000870 provides a more generalized test method covering electronic and optoelectronic components used in telecommunications equipment. This test method also requires the use of six samples. Three samples are stressed with both polarities at sequentially higher voltage levels until one or more failures occur. The other three samples are used to verify the failure level. This technique can identify and possibly discount the effects of cumulative damage due to multiple stresses.

TR-NWT-000870 provides for two test conditions. In one case each non-supply pin (or I/O pin) is stressed individually to all other non-supply or I/O pins connected together while the supply pins are floating. In the second case all non-supply or I/O pins are stressed individually to all power supply pins connected together while all other non-supply pins are floating.

Other Standards:

Department of Defense MIL-STD-883, Method 3015

“Test Method Standard Microcircuits, Electrostatic Discharge Sensitivity Classification” (intended to apply only to microelectronic devices)

JEDEC Solid State Technology Association JESD22-A114-B

“Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)” (method for testing and classifying microcircuits)

Electrostatic Discharge Association ESD STM 5.1-1998

“Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing, Human Body Model (HBM), Component Level” (Component is defined as “An item such as a resistor, diode, transistor, integrated circuit or hybrid circuit”)

These three standards are very similar to TR-NWT-000870, but with an important difference that can significantly impact the cost of testing complex devices. In each case the standards require stressing the non-supply or I/O pins individually to all other non-supply or I/O pins connected together (the same as TR-NWT-000870). The difference is these three standards require that each I/O pin be stressed individually to each independent power supply or ground pin. This is repeated for each independent power supply or ground pin.

For a complex device such as a MSA compliant 300 pin optical transponder, which may have six to ten independent power supply and ground connections, the testing complexity increases significantly when one of these three standards is specified. We typically advise our telecommunications customers to use Telcordia TR-NWT-000870 unless their customer has a compelling reason to specify MIL-STD-883 or one of the other ESD test standards.

We at Silicon Cert will be happy to guide you through the complex standards and help you identify the most appropriate test method for your product application. Please give us a call to discuss your individual ESD testing needs or to request a quote.

Failure Mode Analysis:

If components fail at a lower voltage level than expected during ESD testing, Silicon Cert has the expertise and the equipment to assist in identifying the root cause. This is accomplished through complete failure mode analysis (FMA) utilizing data analysis, electrical testing, and Scanning Electron Microscopy (SEM), providing a comprehensive report of the findings. All to help YOU in providing the finest, high reliability devices for YOUR customer!

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